Improved delay and current models for estimating maximum currents in CMOS VLSI circuits

Author

Kriplani, Harish ; Najm, Farid ; Hajj, Ibrahim

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

Volume

1

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

435

Abstract

Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade both design reliability and performance. Maximum current estimates are needed in the circuit to accurately determine the impact of these problems. In a previous paper by the authors (see Design Automation Conf., p. 2-7, June 8-12, 1992), a pattern-independent, linear time algorithm (iMax) is described that is very effective in estimating the maximum current waveforms at various contact points in the circuit. In the aforementioned paper, the algorithm was demonstrated for simple gate delay and current models. In this paper, we first derive expressions for modeling delays and current waveforms for a general gate and then describe how the algorithm can be extended under more general models

Keywords

CMOS digital integrated circuits; CMOS logic circuits; VLSI; circuit analysis computing; delays; integrated circuit modelling; integrated circuit reliability; logic gates; CMOS VLSI circuits; CMOS gate; CMOS inverter; current models; current waveforms; delay models; gate delay; iMax algorithm; maximum current esimation; pattern-independent linear time algorithm; Algorithm design and analysis; CMOS logic circuits; Delay estimation; Integrated circuit reliability; Inverters; Performance analysis; Propagation delay; Semiconductor device modeling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.408832

Filename

408832