A timing model for VLSI CMOS circuits verification and optimization

Author

Uebel, Luís Felipe ; Bampi, Sergio

Author_Institution

Curso de Pos-Graduacao em Ciencia da Computacao, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil

Volume

1

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

439

Abstract

This paper presents a semi-empirical model (TIME) for timing verification of CMOS VLSI digital circuits. Its novelty lies in the introduction of a new timing parameter (latency time), which is added to the usual ℜC effective time constant. The effects that bear in the delay of all gates are included in the TIME model: type, geometry, body effect of transistors, slope of the gate input signals, capacitance loads and threshold logic voltage (VSW). Results are shown that compare circuit delays, analytically estimated with this model, within 10% of SPICE simulations and with more accuracy than Horowitz´s analytical timing model. Other results illustrate the application of TIME to W-size optimization

Keywords

CMOS digital integrated circuits; CMOS logic circuits; VLSI; circuit analysis computing; circuit optimisation; delays; integrated circuit modelling; timing; TIME model; VLSI CMOS circuits; W-size optimization; capacitance loads; circuit optimization; circuit verification; digital circuits; gate delay; latency time; semi-empirical model; threshold logic voltage; timing model; timing parameter; timing verification; Analytical models; CMOS digital integrated circuits; Delay effects; Delay estimation; Digital circuits; Geometry; Semiconductor device modeling; Solid modeling; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.408833

Filename

408833