Session 10: CMOS devices and technology - Vth variation and scaling

This session reports recent advanced progresses made in the field of Vth variability and scaling-related issues. The first paper reports 0.124 µm² SRAM cell integration using high-K and metal gate allowing significant mismatch improvement. The second paper focuses on 0.128µm² FinFet SRAM cell with proposed integration scheme to reduce Vth variation. The third paper provides optimized guidelines for FinFET SRAM scaling. The fourth paper reports the highest matching performance ever reported in undoped ultra-thin FDSOI MOSFETs. The fifth paper identifies the various components in the Vth variability for thin BOX CMOS devices. The sixth paper is an invited paper focused on the prospects of velocity enhancement and the outlooks for novel channel materials such as Ge and III-V. The seventh paper proposes new effective drive current methodologies to predict performance consistently across wide Vth range.