Signal integrity analysis and optimization of VLSI interconnects using neural network models

Signal integrity issues such as delay and crosstalk are important in designing high-speed printed circuits boards and multichip modules. A complete signal integrity analysis and optimization require repeated simulation of distributed networks which can be very CPU intensive. In this paper an efficient approach is presented using neural network models to describe the signal integrity behaviour of a distributed network. The model is used to formulate a signal integrity optimization problem, replacing exact circuit simulations. This approach has been used in analysis and yield optimization of high-speed VLSI interconnects and is much faster than the standard optimization