Title :
An hierarchical approach to clock routing in high performance systems
Author :
Khan, Wasim ; Madhwapathy, Sreekrishna ; Sherwani, Naveed
Author_Institution :
Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
fDate :
30 May-2 Jun 1994
Abstract :
In this paper, we present an hierarchical clock routing scheme, which minimizes the longest source to sink path, and obtains a path balanced clock tree with minimal total wirelength. Our scheme takes into consideration, the hierarchical design of a circuit. Our approach is applicable to large VLSI circuits and MCM´s. The algorithm has been implemented and experimental results are encouraging
Keywords :
VLSI; circuit layout CAD; digital circuits; digital integrated circuits; integrated circuit layout; multichip modules; network routing; timing; MCM; clock routing; hierarchical design; hierarchical routing scheme; high performance systems; large VLSI circuits; minimal total wirelength; path balanced clock tree; Circuits; Clocks; Costs; Delay; Frequency; Parasitic capacitance; Partitioning algorithms; Routing; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408839
