Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

Highly scaled FinFET SRAM cells, of area down to 0.128 m², were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate V_t variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce V_t variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m² cell, at V_d = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. sigmaV_t of transistors in 0.187 m² cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher sigmaV_t mainly caused by heavy doping into the channel region.