Constraint generation and placement for automatic layout design of analog integrated circuits

Electrical performances of integrated circuits operating at high frequencies, can be significantly degraded by electrical parasitics non intentionally introduced during the layout design. We present here new tools for the automatic constraint driven placement and routing of analog integrated circuits. Furthermore we introduce a new constraint generation program, based on AC analysis in the frequency domain. The constraints produced by this program have been-employed to drive the automatic layout tools, during the experiments here reported. These programs automatically produce the layout of high performance integrated circuits, significantly reducing the electrically effective parasitics due to finite length interconnections