A standardized interface control unit for heterogeneous digital signal processors

An approach is presented for the implementation of high-performance heterogeneous digital signal processors. This approach facilitates tailoring the configuration of the hardware to the signal flow graph of the application. The hardware system comprises heterogeneous processors which are specialized for performing a predefined set of functions. The focus of this research is to solve the communication problems associated with the interconnection of the heterogeneous building blocks to implement application-specific systems. An interface control unit (ICU) architecture is proposed that allows the interconnection of processors with varying speeds and functionalities. A protocol has been developed that facilitates transfer of large data blocks in sparse networks. The hardware design and implementation of the ICU is based on this protocol. The digital design of the ICU is suitable for fabrication as a single VLSI circuit