Session 14: Characterization, reliability, and yield - ESD/memory reliability

The ESD and non-volatile memory reliability session focuses on recent developments in ESD and Latchup protection methodology and reliability challenges for NVMs. The invited talk on the ESD qualification for 45 nm and beyond provides first hand information about the vivid discussion on ESD target levels started in the electronics industry. For 22 nm and beyond FINFET technology might become an option which requires an appropriate ESD protection as discussed by the second paper. The growing awareness of a latchup optimized design is addressed by the study of guard ring interactions and their effect on CMOS Latchup resilience. In the second part of the session, Non-Volatile Memory reliability aspects will be presented, starting with a new method to evaluate the trapped charge distributions in SONOS-type devices. Retention implications will be discussed in this presentation, as well as in the following one, focused on the statistical investigation of leakage current in floating gate cells with a high-k interpoly dielectric. In the last paper of this session, evidence will be provided for bit flips produced in Flash memories by the atmospheric neutrons deriving as ground level byproducts of cosmic ions.