SoC performance evaluation with ArchC and TLM-2.0

Author

Walter, Jorg ; Lenhardt, Jorg ; Schiffmann, Wolfram

Author_Institution

OFFIS Inst. for Inf. Technol., Oldenburg, Germany

fYear

2013

fDate

10-12 July 2013

Firstpage

1

Lastpage

8

Abstract

ArchC is an architecture description language that provides instruction set level simulation and binary tool chain generation. It is based on SystemC and can communicate with other SystemC components using transaction level modeling (TLM). In this article we present an upgrade of ArchC that allows TLM-2.0 usage and makes it available in timed simulations. These extensions enable performance evaluation of complete System-on-Chip designs built around an ArchC processor model. As a proof-of-concept, we examine various TLM-connected memory hierarchies. We outline how model designers can use a combination of fast functional simulation and slow timed simulation to determine an optimal system architecture for a given workload.

Keywords

circuit simulation; hardware description languages; instruction sets; integrated circuit design; system-on-chip; ArchC; SoC performance evaluation; SystemC; TLM-2.0 usage; TLM-connected memory hierarchy; architecture description language; binary tool chain generation; fast functional simulation; instruction set level simulation; optimal system architecture; slow timed simulation; system-on-chip design; transaction level modeling; Hardware; Load modeling; Pipelines; Time-domain analysis; Time-varying systems; Timing; ADL; system-on-chip; transaction level modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on

Conference_Location

Darmstadt

Print_ISBN

978-1-4673-6180-4

Type

conf

DOI

10.1109/ReCoSoC.2013.6581521

Filename

6581521