Design and use of tweakable devices for future logic implementation

Summary form only given. In this era of low power, much of device engineering has focused on constructing devices which offer as good a power-delay tradeoff as possible. However, one should not forget the typical use models of these devices by designers at higher levels of abstraction: namely circuit and physical design. Power optimization tools leverage varying timing requirements of different parts of the design to reduce power by selectively inserting slower devices. The final power-reduction depends on the number and kind of device "variations" available. As a result, we argue that few "good" devices implementable controllably are better than one "great" device for digital logic implementation.