CMOS VLSI implementation of the 2D-DCT with linear processor arrays

Author

Totzek, U. ; Matthiesen, F. ; Wohlleben, P. ; Noll, T.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1990

fDate

3-6 Apr 1990

Firstpage

937

Abstract

The design of a test chip for the computation of the two-dimensional discrete cosine transform (2D-DCT) is described. Different chip architectures based on a matrix formulation of the 2D-DCT algorithm are developed systematically. Circuit and layout for one architecture, selected for a 1.5-μm CMOS test chip, are presented. The test chip computes the DCT and its inverse with high accuracy, meeting the CCITT specification standard, for a block size of 8×8 with a 45-MHz and for a block size of 16×16 with a 22.5-MHz pixel rate under worst-case conditions

Keywords

CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; multiprocessing systems; transforms; 1.5 micron; 22.5 MHz; 2D-DCT algorithm; 4.5 MHz; CCITT specification standard; CMOS VLSI implementation; chip architectures; image coding; linear processor arrays; matrix formulation; two-dimensional discrete cosine transform; CMOS process; Circuit testing; Clocks; Computer architecture; Concurrent computing; Digital signal processing chips; Discrete cosine transforms; Research and development; Vectors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.116011

Filename

116011