Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics

Author

Miyamura, Makoto ; Nagumo, Toshiharu ; Takeuchi, Kiyoshi ; Takeda, Koichi ; Hane, Masami

Author_Institution

Device Platforms Res. Labs., NEC Corp., Sagamihara

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

Enhancement mechanism of Vth fluctuation in saturation region is analyzed through addressable transistor array measurement and 3D Monte-Carlo TCAD simulation. It was confirmed that random dopant fluctuation (RDF) in heavily doped halo devices enhances source-drain asymmetry, resulting in non-Gaussian distributions of DIBL and saturation Vth (Vth_sat). The measured DIBL behavior was accurately modeled and implemented in statistical circuit simulation, to evaluate the impact on SRAM stability. Optimization of halo for mitigating RDF is important for achieving aggressively scaled SRAM cells.

Keywords

CAD; Monte Carlo methods; SRAM chips; circuit simulation; 3D Monte-Carlo TCAD simulation; SRAM stability; addressable transistor array measurement; circuit characteristics; drain bias; enhancement mechanism; random dopant fluctuation; saturation region; source-drain asymmetry; threshold voltage fluctuation; Atomic measurements; Circuit simulation; Fluctuations; Laboratories; Large scale integration; National electric code; Random access memory; Resource description framework; Semiconductor device modeling; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796721

Filename

4796721