DocumentCode :
2930309
Title :
Hardware implementations of the WG-5 cipher for passive RFID tags
Author :
Aagaard, Mark D. ; Guang Gong ; Mota, Rajesh K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
fYear :
2013
fDate :
2-3 June 2013
Firstpage :
29
Lastpage :
34
Abstract :
This paper presents two versions of a Welch-Gong cipher designed for use in passive RFID tags. The low-cost and low-power requirements for passive RFID tags impose stringent design constraints for the chips used in the tags. The WG5-80(x) cipher operates over the finite field F25, and has an 80-bit secret key and 80-bit initialization vector. WG5-80(x11) is the same as WG5-80(x), but includes a decimation function of x11, which increases the linear complexity at the cost of losing the 1-order resiliency property that is inherent in the WG-transform. Both ciphers can be implemented using parallel LFSRs to provide throughputs ranging from one to twenty-five bits per clock cycle. On a 130 nm fabrication process with a clockspeed of 100 kHz and a throughput of 100 kbps, WG5-80(x) has an area of 1229 GE (gate equivalents) and a power consumption of 0.78 μW. The linear complexity of the cipher is 217. The corresponding numbers for WG5-80(x11) are 1235GE, 0.79 μW, and 222. This paper presents results for a 130 nm and a 180 nm process, and data rates of 100 kbps and 200 kbps. The combined area and power results for the WG5 ciphers are approximately 5% better than previous results for low-data-rate ciphers. In addition, WG-ciphers offer mathematically guaranteed randomness and cryptographic properties not provided by other ciphers.
Keywords :
cryptography; radiofrequency identification; transforms; WG-5 cipher; WG-transform; Welch-Gong cipher; bit rate 100 kbit/s; bit rate 200 kbit/s; cryptographic properties; fabrication process; frequency 100 kHz; hardware implementations; initialization vector; linear complexity; low-cost requirements; low-data-rate ciphers; low-power requirements; parallel LFSR; passive RFID tags; power 0.78 muW; power 0.79 muW; secret key; size 130 nm; size 180 nm; stringent design constraints; word length 80 bit; Ciphers; Clocks; Complexity theory; Correlation; Polynomials; Rain;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2013 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4799-0559-1
Type :
conf
DOI :
10.1109/HST.2013.6581561
Filename :
6581561
Link To Document :
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