A VLSI systolic array architecture for Lempel-Ziv-based data compression

We present a parallel algorithm, architecture, and implementation for Lempel-Ziv-based data compression. The parallel algorithm exhibits a regular structure and is well suited for parallel VLSI array implementation. Based on our parallel algorithm, a word-parallel systolic array has been developed using systematic design methodologies. Compared to a recent systolic architecture, our array structure is substantially faster, with latency of N/2+M compared to 2N+M where M is the maximum allowable length of symbols to be encoded at each encoding step and N is the length of symbols in an encoding buffer which have already been encoded. Furthermore the architecture consumes significantly less area and has a faster clock rate