Title :
Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing
Author :
Denk, Tracy C. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
30 May-2 Jun 1994
Abstract :
This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform
Keywords :
FIR filters; VLSI; band-pass filters; delays; transforms; two-dimensional digital filters; wavelet transforms; 2D discrete wavelet transforms; FIR filters; architecture design; data format converters; lapped block processing; life-time analysis; on-chip line delays; Computer architecture; Delay lines; Discrete cosine transforms; Discrete transforms; Discrete wavelet transforms; Filter bank; Filtering; Finite impulse response filter; Propagation delay; Registers;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409107
