DocumentCode :
293073
Title :
A new design for a frame sampling synchronizer
Author :
Walker, Jacqueline ; Cantoni, Antonio
Author_Institution :
Telecommun. Res. Inst., Curtin Univ. of Technol., Bentley, WA, Australia
Volume :
3
fYear :
1994
fDate :
30 May-2 Jun 1994
Firstpage :
97
Abstract :
This paper proposes a new design for a frame sampling synchronizer and gives some typical applications for the device. It also discusses metastability which arises in the system due to the existence of asynchronous inputs. The motivation for the new design, details of the design and its modelling are also covered. Finally the jitter generated by the synchronizer is analysed
Keywords :
asynchronous circuits; circuit stability; digital communication; jitter; synchronisation; asynchronous inputs; design modelling; digital communication; frame sampling synchronizer; jitter; metastability; timing; Australia; Clocks; Counting circuits; Encoding; Frequency synchronization; Jitter; Metastasis; Repeaters; Sampling methods; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
Type :
conf
DOI :
10.1109/ISCAS.1994.409112
Filename :
409112
Link To Document :
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