Title :
Application specific memories for ATM packet switching
Author :
Dickinson, A.G. ; Nicol, C.J. ; Rao, S.K. ; Hatamian, M.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
30 May-2 Jun 1994
Abstract :
The constrained data access patterns occurring within memory-based packet switches permit the design of application specific SRAM devices that may outperform generic SRAM parts in switch applications. We describe two such devices: one reads and writes a single location in a single 10 ns cycle; the other uses a systolic approach to pipeline accesses in a large array resulting in a 5 ns cycle time
Keywords :
SRAM chips; application specific integrated circuits; asynchronous transfer mode; memory architecture; packet switching; pipeline processing; systolic arrays; 10 ns; ATM packet switching; SRAM devices; access pipelining; application specific memories; constrained data access patterns; cycle time; memory-based packet switches; single location; switch applications; systolic approach; Application software; Asynchronous transfer mode; Circuits; Clocks; Computer architecture; Delay; Packet switching; Random access memory; Read-write memory; Switches;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409132
