3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.