Title :
Parallel architectures of 3-step search block-matching algorithm for video coding
Author :
Jong, Her-Ming ; Chen, Liang-Gee ; Chiueh, Tzi-Dar
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
30 May-2 Jun 1994
Abstract :
This paper describes fully pipelined parallel architectures for the 3-step search block-matching motion estimation algorithm. Difficulties of this algorithm in hardware implementation were overcome by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed architectures provide efficient solutions for real-time motion estimations required by various video applications
Keywords :
data compression; image matching; motion estimation; parallel algorithms; parallel architectures; pipeline processing; real-time systems; video coding; 3-step search block-matching algorithm; motion estimation algorithm; pipelined parallel architectures; real-time motion estimation; video coding; Bandwidth; Computational efficiency; Computer architecture; Costs; Hardware; Motion estimation; Parallel architectures; Very large scale integration; Video coding; Video compression;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409144
