A pipelined systolic arrays architecture for the hierarchical block-matching algorithm

Author

Kim, Hyung Chul ; Maeng, Seung Ryoul

Author_Institution

Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

Volume

3

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

221

Abstract

This paper presents a pipelined architecture for the hierarchical block-matching motion estimation algorithm (HBMA). The hierarchical style leads to an enormous computation and complex data flow between hierarchy levels. Each stage of the proposed architecture consists of a systolic array for block-matching and an interpolation unit for bilinear interpolation. The interpolation unit regulates also the data flow suitable for fully synchronous operation. The performance analysis shows that the proposed architecture gains nearly linear speedup, thus making HBMA suitable for real time operation

Keywords

image matching; interpolation; motion estimation; parallel algorithms; performance evaluation; real-time systems; systolic arrays; bilinear interpolation; fully synchronous operation; hierarchical block-matching algorithm; image processing; interpolation unit; motion estimation algorithm; performance analysis; pipelined systolic arrays architecture; real time operation; Computer architecture; Computer science; Interpolation; Motion estimation; Parallel processing; Performance analysis; Performance gain; Pipelines; Systolic arrays; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409147

Filename

409147