A pipelined systolic arrays architecture for the hierarchical block-matching algorithm

This paper presents a pipelined architecture for the hierarchical block-matching motion estimation algorithm (HBMA). The hierarchical style leads to an enormous computation and complex data flow between hierarchy levels. Each stage of the proposed architecture consists of a systolic array for block-matching and an interpolation unit for bilinear interpolation. The interpolation unit regulates also the data flow suitable for fully synchronous operation. The performance analysis shows that the proposed architecture gains nearly linear speedup, thus making HBMA suitable for real time operation