Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

Author

Hoentschel, J. ; Wei, A. ; Wiatr, M. ; Gehring, A. ; Scheiper, T. ; Mulfinger, R. ; Feudel, T. ; Lingner, T. ; Poock, A. ; Muehle, S. ; Krueger, C. ; Herrmann, T. ; Klix, W. ; Stenzel, R. ; Stephan, R. ; Huebler, P. ; Kammler, T. ; Shi, P. ; Raab, M. ; Gr

Author_Institution

AMD Fab 36 LLC & Co. KG, Dresden

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of asymmetric transistors showed a speed benefit of 12%, at matched yield and improved reliability.

Keywords

CMOS integrated circuits; microprocessor chips; silicon-on-insulator; transistors; SOI CMOS technologies; asymmetric transistors; drain extension transistors; high performance microprocessors; size 45 nm; size 65 nm; source extension transistors; voltage 1 V; CMOS technology; Capacitance; Doping profiles; Electrostatics; Implants; MOS devices; Microprocessors; Physics; Tensile stress; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796775

Filename

4796775