DocumentCode
293130
Title
Systematic design of multi-modulus/multi-function Residue Number System processors
Author
Paliouras, V. ; Stouraitis, T.
Author_Institution
Dept. of Electr. Eng., Patras Univ., Greece
Volume
4
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
79
Abstract
A methodology for the design of novel Residue Number System (RNS) processors is presented. It results in ROM-less processors, which perform basic residue arithmetic algorithms in more than one moduli channel, either serially or concurrently. Moreover, the proposed architectures achieve area savings, while operating at a high throughput rate. Criteria for selecting the most appropriate moduli of operation are presented. The derived architectures are compared to memory- and full adder-based designs
Keywords
adders; parallel architectures; residue number systems; ROM-less processors; adders; area savings; moduli of operation; multi-modulus/multi-function RNS processors; residue number system; throughput rate; Arithmetic; Bismuth; Computer architecture; Design methodology; Error correction; Fault detection; Polynomials; Process design; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409201
Filename
409201
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