DocumentCode
2931340
Title
A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array
Author
Natarajan, S. ; Armstrong, M. ; Bost, M. ; Brain, R. ; Brazier, M. ; Chang, C.-H. ; Chikarmane, V. ; Childs, M. ; Deshpande, H. ; Dev, K. ; Ding, G. ; Ghani, T. ; Golonzka, O. ; Han, W. ; He, J. ; Heussner, R. ; James, R. ; Jin, I. ; Kenyon, C. ; Klopcic,
fYear
2008
fDate
15-17 Dec. 2008
Firstpage
1
Lastpage
3
Abstract
A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum2 cell size, containing >1.9 billion transistors.
Keywords
SRAM chips; elemental semiconductors; high-k dielectric thin films; immersion lithography; logic gates; semiconductor device reliability; silicon; transistors; work function; 2nd-generation high-k + metal-gate transistors; 4th-generation strained silicon; NMOS; PMOS; SRAM; channel strain; immersion lithography; logic; patterning; size 32 nm; size 9 A; storage capacity 291 Mbit; wavelength 193 nm; workfunction; Capacitive sensors; High K dielectric materials; High-K gate dielectrics; Lithography; Logic; MOS devices; Random access memory; Silicon; Testing; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location
San Francisco, CA
ISSN
8164-2284
Print_ISBN
978-1-4244-2377-4
Electronic_ISBN
8164-2284
Type
conf
DOI
10.1109/IEDM.2008.4796777
Filename
4796777
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