Title :
Unification of speed, power, area, and reliability in CMOS tapered buffer design
Author :
Cherkauer, Brian S. ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
fDate :
30 May-2 Jun 1994
Abstract :
Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffer design. Each places a separate, often conflicting constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are developed for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability and a two-component physical area model. Each performance criterion is independently investigated and analyzed, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. These disparate approaches to tapered buffer design are unified into a convenient, integrated design methodology
Keywords :
CMOS logic circuits; buffer circuits; delays; hot carriers; integrated circuit design; integrated circuit reliability; CMOS tapered buffer; buffer design equations; circuit speed; design tradeoffs; hot-carrier reliability; integrated design methodology; power dissipation; propagation delay; split-capacitor model; system reliability; two-component physical area model; Capacitance; Circuits; Design methodology; Equations; Hot carriers; Power dissipation; Power system modeling; Power system reliability; Propagation delay; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409210
