Tree-structure architecture and VLSI implementation for vector quantization algorithms

Author

Ku, Chung-Wei ; Chen, Liang-Gee ; Chiueh, Tzi-Dar ; Jong, Her-Ming

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

4

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

139

Abstract

A tree-structure based architecture for vector quantization (VQ) is proposed and implemented by VLSI in this paper, The proposed folded-tree architecture is designed by 0.8 μm CMOS VLSI technology. The die size is 4.65×5.21 mm² and estimated clock rate is about 34 MHz, which satisfies most real-time applications. Since it is basically a mean squared error computation circuit, various kinds of VQ algorithms can apply on the proposed architecture

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; integrated circuit layout; real-time systems; vector quantisation; 0.8 micron; 34 MHz; CMOS VLSI technology; VLSI implementation; VQ algorithms; folded-tree architecture; mean squared error computation circuit; real-time applications; tree-structure architecture; vector quantization algorithms; Algorithm design and analysis; CMOS technology; Computer architecture; Delay; Encoding; Hardware; Image coding; Vector quantization; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409216

Filename

409216