A low-power and low-complexity DCT/IDCT VLSI architecture based on backward Chebyshev recursion

Author

Wu, An-Yeu ; Liu, K. J Ray

Author_Institution

Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

Volume

4

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

155

Abstract

A low-power parallel VLSI structure for DCT/IDCT is proposed. By treating the transformations as the evaluation of the Chebyshev series, and exploiting the Backward Chebyshev Recursion (BCR), we can reduce the total number of multipliers (N+1 for IDCT, 2N-2 for DCT). The property of BCR is also used to compute the DCT/IDCT through the down-sampled even and odd sequences. Since the operation frequency for the down-sampled sequences is two times slower, the speed penalty caused by the low-voltage design can be compensated at the architectural level. The total multipliers required for the low-power design is only 2N+1 for IDCT and 3N-3 for DCT. Extension to downsampling-by-4 is also achievable at a reasonable increase in hardware complexity

Keywords

CMOS digital integrated circuits; Chebyshev approximation; VLSI; digital signal processing chips; discrete cosine transforms; parallel algorithms; parallel architectures; Chebyshev series; DCT; backward Chebyshev recursion; down-sampled even sequences; down-sampled odd sequences; inverse DCT; low-complexity VLSI architecture; low-power operation; low-voltage design; parallel VLSI structure; Chebyshev approximation; Circuits; Discrete cosine transforms; Energy consumption; Frequency estimation; Hardware; Personal communication networks; Polynomials; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409221

Filename

409221