DocumentCode
293158
Title
A digit-serial architecture for gray-scale morphological filtering
Author
Lucke, Lori ; Chakrabarti, Chaitali
Author_Institution
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume
4
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
207
Abstract
We present a digit-serial architecture for gray-scale morphological operations which operates on radix-2 redundant numbers. We present new implementations of a redundant number adder and maximum unit used in the morphological dilation unit. These new designs have areas comparable to 2´s complement implementations, but have significantly smaller latencies
Keywords
CMOS digital integrated circuits; VLSI; computer architecture; computer vision; digital signal processing chips; feature extraction; image processing equipment; redundant number systems; CMOS IC; DSP chip; digit-serial architecture; gray-scale morphological filtering; latency reduction; morphological dilation unit; radix-2 redundant numbers; Arithmetic; Computer architecture; Delay; Feature extraction; Filtering; Gray-scale; Logic functions; Machine vision; Morphological operations; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409233
Filename
409233
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