Optimization of real-time VLSI architectures for distributed arithmetic-based algorithms: application to HDTV filters

In order to implement the distributed arithmetic-based inner product, we propose two different architectures: ROM-based architecture and hardwired architecture. To define the optimal VLSI architecture, we consider all possible input data parallelisations: from bit-serial to bit-parallel. Then, for each parallelisation, we consider all possible partitions of the lookup-table. For both ROM-based and hardwired architectures, expressions are developed for area and speed, which allow us to have an explicit formulation of the area-speed tradeoff. Then, for given application constraints (inner product size and input data bandwidth), we exhibit the optimal architectural parameters that provide the smallest chip area. Finally, we show that, at any given application constraints, the hardwired architecture provides a smaller area than the ROM-based architecture