• DocumentCode
    2931852
  • Title

    Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference

  • Author

    Namasivayam, Vasanth Krishna ; Pathak, Animesh ; Prasanna, Viktor K.

  • Author_Institution
    Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA
  • fYear
    2006
  • fDate
    Oct. 2006
  • Firstpage
    167
  • Lastpage
    176
  • Abstract
    We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inference. We explore parallelism during the process of moralization, triangulation, clique identification, junction tree construction and potential table calculation. For an arbitrary Bayesian network with n vertices using p processors, the worst-case running time is shown to be O(n2w/p+-wrwn/p+n log p), where w is the clique width and r is the number of states of the random variables. Our algorithm is scalable over 1 les p les nw/log n. We have implemented our parallel algorithm using OpenMP and experimented with up to 128 processors. We consider three types of Bayesian networks: linear, balanced and random. While the state of the art PNL library implementation does not scale, we achieve speedups of 31, 29 and 24 for the above graphs respectively on the DataStar cluster at San Diego Supercomputing Center
  • Keywords
    belief networks; computational complexity; parallel algorithms; trees (mathematics); OpenMP; balanced Bayesian network; clique identification; computational complexity; exact inference; junction tree construction; junction tree conversion; linear Bayesian network; parallel algorithm; potential table calculation; random Bayesian network; triangulation; Application software; Artificial intelligence; Bayesian methods; Computer networks; Inference algorithms; Libraries; Medical diagnosis; Parallel algorithms; Parallel processing; Random variables;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing, 2006. SBAC-PAD '06. 18TH International Symposium on
  • Conference_Location
    Ouro Preto
  • ISSN
    1550-6533
  • Print_ISBN
    0-7695-2704-3
  • Type

    conf

  • DOI
    10.1109/SBAC-PAD.2006.26
  • Filename
    4032429