• DocumentCode
    293198
  • Title

    Storage enhancement techniques for digital memory based, analog computational engines

  • Author

    Miwa, Hitoshi ; Yang, Kewei ; Pouliquen, Philippe O. ; Kumar, Nagendra ; Andreou, Andreas G.

  • Author_Institution
    Device Dev. Center, Hitachi Ltd., Tokyo, Japan
  • Volume
    5
  • fYear
    1994
  • fDate
    30 May-2 Jun 1994
  • Firstpage
    45
  • Abstract
    We propose a multi-chip organization for Winner-Takes-All associative memory (WAM) systems for processing sensory information such as speech. Using mixed analog/digital circuit techniques, this hardware solution has great advantages, such as portable size, low power consumption for battery operation and low cost for personal use. A Winner-offset circuit performs a close competitor detection and process variation adjustment to enhance existing memory capacity. We report on experimental data from test chips. Maximum capability of the circuit is estimated based on a process variation model of MOS transistors
  • Keywords
    application specific integrated circuits; content-addressable storage; memory architecture; mixed analogue-digital integrated circuits; neural chips; ASIC; analog computational engines; close competitor detection; digital memory; mixed analog/digital circuit techniques; multi-chip organization; neural systems; power consumption; process variation adjustment; sensory information; winner-takes-all associative memory; Analog computers; Associative memory; Batteries; Circuit testing; Costs; Energy consumption; Engines; Hardware; Power system modeling; Speech processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
  • Conference_Location
    London
  • Print_ISBN
    0-7803-1915-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1994.409295
  • Filename
    409295