Implementation of a parallel Jacobi algorithm on multiple DSP96002 digital signal processors

A multiprocessor architecture is presented using a number of Motorola DSP96002 digital signal processors in parallel with no required glue logic. It is shown how this configuration can be used efficiently to implement a parallel Jacobi algorithm. Processor overhead is practically negligible because of the DSP96002 dual bus structure, its independent DMA channels, and its host interfaces. The example discussed (eigenvalues decomposition) is only one of many applications that can benefit from the architecture. It is shown how the multiprocessing features of the DSP96002 can naturally lead to relatively inexpensive implementations of high-speed number crunchers, offering literally hundreds or even thousands of megaFLOPS in one low-power, compact system