• DocumentCode
    2932145
  • Title

    TDDB in the presence of interface states: Implications for the PMOS reliability margin

  • Author

    Nigam, T. ; Peumans, P.

  • fYear
    2008
  • fDate
    15-17 Dec. 2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The reduced voltage scaling parameter for PMOS TDDB at low voltages is a concern for ultra-thin gate oxides. We show that it is caused by a change in breakdown statistics due to additional interface defects generated by cold holes. This has important implications for product lifetime at low failure fractions and large areas.
  • Keywords
    MOSFET; electric breakdown; interface states; semiconductor device reliability; PMOS reliability margin; breakdown statistics; cold holes; interface states; time dependent dielectric breakdown; ultra-thin gate oxides; Breakdown voltage; Dielectric breakdown; Electric breakdown; Interface states; MOS devices; Niobium compounds; Statistics; Stress; Temperature; Titanium compounds;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    8164-2284
  • Print_ISBN
    978-1-4244-2377-4
  • Electronic_ISBN
    8164-2284
  • Type

    conf

  • DOI
    10.1109/IEDM.2008.4796814
  • Filename
    4796814
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2932145