DocumentCode
2932258
Title
6F2 buried wordline DRAM cell for 40nm and beyond
Author
Schloesser, T. ; Jakubowski, F. ; Kluge, J.V. ; Graham, A. ; Slesazeck, S. ; Popp, M. ; Baars, P. ; Muemmler, K. ; Moll, P. ; Wilson, K. ; Buerke, A. ; Koehler, D. ; Radecker, J. ; Erben, E. ; Zimmermann, U. ; Vorrath, T. ; Fischer, B. ; Aichmayr, G. ; Ag
Author_Institution
Qimonda Dresden GmbH & Co. OHG, Dresden
fYear
2008
fDate
15-17 Dec. 2008
Firstpage
1
Lastpage
4
Abstract
We present a 46 nm 6F2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013 mum2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting in an excellent array performance. The array device can be scaled down to 30 nm without compromising its performance.
Keywords
DRAM chips; capacitance; integrated circuit interconnections; reliability; titanium compounds; tungsten; 6F2 buried wordline DRAM cell; Si; TiN-W; array transistors; high array device on-current; low resistive interconnect; metal gate; parameter variability; parasitic capacitances; reliability; size 46 nm; Capacitors; Dielectric devices; Electric resistance; Energy consumption; Implants; Lithography; Low voltage; Parasitic capacitance; Random access memory; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location
San Francisco, CA
ISSN
8164-2284
Print_ISBN
978-1-4244-2377-4
Electronic_ISBN
8164-2284
Type
conf
DOI
10.1109/IEDM.2008.4796820
Filename
4796820
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