Title :
6F2 buried wordline DRAM cell for 40nm and beyond
Author :
Schloesser, T. ; Jakubowski, F. ; Kluge, J.V. ; Graham, A. ; Slesazeck, S. ; Popp, M. ; Baars, P. ; Muemmler, K. ; Moll, P. ; Wilson, K. ; Buerke, A. ; Koehler, D. ; Radecker, J. ; Erben, E. ; Zimmermann, U. ; Vorrath, T. ; Fischer, B. ; Aichmayr, G. ; Ag
Author_Institution :
Qimonda Dresden GmbH & Co. OHG, Dresden
Abstract :
We present a 46 nm 6F2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013 mum2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting in an excellent array performance. The array device can be scaled down to 30 nm without compromising its performance.
Keywords :
DRAM chips; capacitance; integrated circuit interconnections; reliability; titanium compounds; tungsten; 6F2 buried wordline DRAM cell; Si; TiN-W; array transistors; high array device on-current; low resistive interconnect; metal gate; parameter variability; parasitic capacitances; reliability; size 46 nm; Capacitors; Dielectric devices; Electric resistance; Energy consumption; Implants; Lithography; Low voltage; Parasitic capacitance; Random access memory; Tin;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796820
