• DocumentCode
    2932416
  • Title

    Good 150°C retention and fast erase characteristics in charge-trap-engineered memory having a scaled Si3N4 layer

  • Author

    Lin, S.H. ; Chin, Albert ; Yeh, F.S. ; McAlister, S.P.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
  • fYear
    2008
  • fDate
    15-17 Dec. 2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    We report a new charge-trap-engineered flash non-volatile memory that has combined 5 nm Si3N4 and 0.9 nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150degC under a 100 mus and plusmn16 V P/E, this device showed good device integrity of a 5.6 V initial DeltaVth window and 3.8 V 10-year extrapolated retention window. These data are better than the 3.3 V initial DeltaVth and 1.7 V 10-year data for a similar structure not having the extra HfON layer.
  • Keywords
    hafnium compounds; random-access storage; silicon compounds; charge-trap-engineered flash non-volatile memory; device integrity; double-barrier layers; double-tunnel layers; size 0.9 nm; size 5 nm; temperature 150 degC; trapping layers; Aluminum oxide; Atherosclerosis; Channel bank filters; Councils; Dielectrics; Electron traps; MONOS devices; MOSFET circuits; Nonvolatile memory; SONOS devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    8164-2284
  • Print_ISBN
    978-1-4244-2377-4
  • Electronic_ISBN
    8164-2284
  • Type

    conf

  • DOI
    10.1109/IEDM.2008.4796829
  • Filename
    4796829
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2932416