DocumentCode
293255
Title
Error analysis of parallel analogue to digital converters
Author
Fernandes, Jorge R. ; Silva, Manuel M.
Author_Institution
INESC, Lisbon, Portugal
Volume
5
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
341
Abstract
For full-parallel, 2-step parallel, and pipelined parallel ADCs (Analogue to Digital Converters) we establish the relationship between the comparator´s input offset voltage and the yield. The yield is defined by three different criteria: absence of missing codes, and either integral or differential nonlinearity below a specific value. The results obtained are confirmed by computer statistical simulation
Keywords
analogue-digital conversion; circuit analysis computing; comparators (circuits); digital simulation; error analysis; integrated circuit yield; parallel processing; pipeline processing; comparator; differential nonlinearity; error analysis; full-parallel convertors; input offset voltage; missing code absence; parallel analogue to digital converters; pipelined ADCs; statistical simulation; two-step parallel convertors; yield; Analog-digital conversion; Circuits; Code standards; Computational modeling; Computer simulation; Energy consumption; Error analysis; Pipelines; Virtual reality; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409377
Filename
409377
Link To Document