Physics-based compact model of III-V heterostructure FETs for digital logic applications

Author

Oh, Saeroonter ; Wong, H. S Philip

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA

fYear

2008

fDate

15-17 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

A physics-based analytical compact model of InGaAs FETs for logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.

Keywords

CMOS integrated circuits; III-V semiconductors; field effect logic circuits; field effect transistors; gallium arsenide; indium compounds; integrated circuit design; integrated circuit modelling; 2D potential profile information; III-V heterostructure FET; InGaAs; circuit-level performance; digital circuit design; digital logic applications; physics-based compact model; time-consuming computation; Analytical models; Digital circuits; Energy capture; FETs; HEMTs; III-V semiconductor materials; Indium gallium arsenide; Logic; MODFETs; Parameter extraction;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Conference_Location

San Francisco, CA

ISSN

8164-2284

Print_ISBN

978-1-4244-2377-4

Electronic_ISBN

8164-2284

Type

conf

DOI

10.1109/IEDM.2008.4796841

Filename

4796841