Title :
Effective reduction of threshold voltage variability and standby leakage using advanced co-implantation and laser anneal for low power applications
Author :
Lee, Ho ; Rhee, Hwa Sung ; Yi, Ji Hye ; Kim, Myung Sun ; Chung, Hoi Sung ; Kim, Min Sun ; Lim, Sun Me ; Kim, Yong Shik ; Park, Moon Han ; Lee, Nae-In ; Yoon, Jong Shik
Author_Institution :
Syst. LSI Div., Samsung Electron. Co., Ltd., Yongin
Abstract :
We have successfully reduced threshold voltage variation by combination of co-implantation and laser spike anneal on 45 nm low power SoC platform with conventional poly-Si/SiON gate stack. Doping profiles of CMOSFET channel is modulated through co-implantation of diffusion suppressor. We have explored the possibility of cluster carbon doping in order to minimize junction leakage degradation. Systematic junction profile design for n- and pFET enables us to reduce random dopant variation significantly without compromising standby leakage, drive current and gate oxide integrity, which finally contributes to RO ~5% performance improvement at equivalent Iddq and ensures high yield of SRAM array by reducing beta and gamma ratio variation.
Keywords :
MOSFET; SRAM chips; elemental semiconductors; low-power electronics; semiconductor doping; semiconductor lasers; silicon; system-on-chip; CMOSFET channel; SRAM array; Si-SiON; advanced co-implantation; cluster carbon doping; doping profiles; laser anneal; low power SoC platform; low power applications; nFET; pFET; size 45 nm; standby leakage; systematic junction profile design; threshold voltage variability; Annealing; CMOS technology; Degradation; Doping; Implants; Power lasers; Random access memory; Solid lasers; Sun; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796849