Effective reduction of threshold voltage variability and standby leakage using advanced co-implantation and laser anneal for low power applications

We have successfully reduced threshold voltage variation by combination of co-implantation and laser spike anneal on 45 nm low power SoC platform with conventional poly-Si/SiON gate stack. Doping profiles of CMOSFET channel is modulated through co-implantation of diffusion suppressor. We have explored the possibility of cluster carbon doping in order to minimize junction leakage degradation. Systematic junction profile design for n- and pFET enables us to reduce random dopant variation significantly without compromising standby leakage, drive current and gate oxide integrity, which finally contributes to RO ~5% performance improvement at equivalent Iddq and ensures high yield of SRAM array by reducing beta and gamma ratio variation.