DocumentCode :
29329
Title :
Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience
Author :
Choudhury, Mihir R. ; Chandra, Vishal ; Aitken, R.C. ; Mohanram, Kartik
Author_Institution :
IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
Volume :
63
Issue :
2
fYear :
2014
fDate :
Feb. 2014
Firstpage :
497
Lastpage :
509
Abstract :
As dynamic variability increases with CMOS scaling, it is essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Three sequential circuit elements are described: TIMBER flip-flop, dedicated TIMBER flip-flop, and TIMBER latch. The TIMBER flip-flop uses two master latches and one slave latch to mask timing errors by borrowing discrete units of time from successive pipeline stages. It can be simplified to a dedicated TIMBER flip-flop that uses only two latches for time-borrowing (TB) at the expense of the flexibility of configuration as a conventional master-slave flip-flop. The TIMBER latch masks timing errors through continuous time-borrowing from successive pipeline stages, and supports runtime configuration as a conventional master-slave flip-flop. The TIMBER latch´s continuous time-borrowing capability provides better time-borrowing capabilities at lower hardware cost, but the TIMBER flip-flop´s discrete time-borrowing capability preserves the edge triggering property of a flip-flop, thus blocking the propagation of glitches and spurious transitions. In addition to evaluating the overhead and tradeoffs of TIMBER-based error masking on an industrial processor, the three circuits were also prototyped on an FPGA and their timing error masking capability was validated using a two-stage pipeline test structure.
Keywords :
CMOS logic circuits; field programmable gate arrays; flip-flops; integrated circuit reliability; integrated circuit yield; logic design; CMOS scaling; FPGA; TIMBER latch masks timing errors; TIMBER-based error masking; continuous time-borrowing capability; dedicated TIMBER flip-flop; design-time timing margins; discrete time-borrowing capability; dynamic variability; edge triggering property; glitch propagation; hardware prototyping; industrial processor; master latches; master-slave flip-flop; online techniques; online timing error resilience; operation reliability; performance improvement; power consumption; runtime configuration; sequential circuit elements; slave latch; successive pipeline stages; time-borrowing circuit designs; timing errors masking; timing margin recovery; two-stage pipeline test structure; yield; Clocks; Delay; Error correction; Image edge detection; Latches; Pipelines; Clocks; Delay; Error correction; Error-checking; Image edge detection; Latches; Pipelines; fault-tolerance; reliability; testing;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2012.190
Filename :
6257368
Link To Document :
بازگشت