Reconfigurable embedded system architecture for next-generation Neural Signal Processing

Author

Balasubramanian, Karthikeyan ; Obeid, Iyad

Author_Institution

Neural Instrum. Lab., Temple Univ., Philadelphia, PA, USA

fYear

2010

fDate

Aug. 31 2010-Sept. 4 2010

Firstpage

1691

Lastpage

1694

Abstract

This work presents a new architectural framework for next generation Neural Signal Processing (NSP). The essential features of the NSP hardware platform include scalability, reconfigurability, real-time processing ability and data storage. This proposed framework has been implemented in a proof-of-concept NSP prototype using an embedded system architecture synthesized in a Xilinx^®Virtex^®5 development board. The prototype includes a threshold-based spike detector and a fuzzy logic-based spike sorter.

Keywords

bioelectric potentials; biomedical electronics; digital signal processing chips; embedded systems; field programmable gate arrays; fuzzy logic; medical signal processing; neurophysiology; reconfigurable architectures; FPGA; data storage; embedded system architecture; fuzzy logic-based spike sorter; next generation neural signal processing; real-time processing; reconfigurability; scalability; threshold-based spike detector; Embedded systems; Field programmable gate arrays; Hardware; Microprogramming; Real time systems; Signal processing; Signal processing algorithms; Action Potentials; Animals; Computing Methodologies; Electroencephalography; Equipment Design; Equipment Failure Analysis; Humans; Neurons; Signal Processing, Computer-Assisted;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering in Medicine and Biology Society (EMBC), 2010 Annual International Conference of the IEEE

Conference_Location

Buenos Aires

ISSN

1557-170X

Print_ISBN

978-1-4244-4123-5

Type

conf

DOI

10.1109/IEMBS.2010.5626833

Filename

5626833