DocumentCode
2932949
Title
0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications
Author
Menou, N. ; Wang, X.P. ; Kaczer, B. ; Polspoel, W. ; Popovici, M. ; Opsomer, K. ; Pawlak, M.A. ; Knaepen, W. ; Detavernier, C. ; Blomberg, T. ; Pierreux, D. ; Swerts, J. ; Maes, J.W. ; Favia, P. ; Bender, H. ; Brijs, B. ; Vandervorst, W. ; Van Elshocht, S
Author_Institution
IMEC, Leuven
fYear
2008
fDate
15-17 Dec. 2008
Firstpage
1
Lastpage
4
Abstract
We demonstrate for the first time record low Leakage-EOT (3.5 times 10-7 A/cm2 at 1V, EOT=0.49 nm) MIM capacitors fabricated using a low temperature (250degC) ALD SrTiO3 (STO) deposition process on ALD TiN bottom electrode. While most previous work on STO used deposition techniques not compatible with high aspect ratio DRAM applications, recent work on ALD STO showed promise on noble-like metal electrodes (Ru, Pt) [1,2]. In this work, a low temperature ALD process with alternative precursor set and carefully optimized deposition and processing conditions enables the use of low-cost, manufacturable-friendly TiN electrode MIMcaps for future DRAM nodes. Composition (Sr-rich) and process optimization allowed minimization of interfacial EOT penalties and leakage reduction by decreasing the density of leakier STO grains.
Keywords
DRAM chips; MIM devices; atomic layer deposition; capacitors; strontium compounds; tin compounds; ALD; DRAM nodes; SrTiO3-TiN; aspect ratio; interfacial EOT penalties; leakage reduction; low leakage-EOT MIM capacitors; metal electrodes; size 0.49 nm; temperature 250 degC; Annealing; Atomic layer deposition; Crystallization; Electrodes; MIM capacitors; Random access memory; Strontium; Temperature; Tin; Water;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location
San Francisco, CA
ISSN
8164-2284
Print_ISBN
978-1-4244-2377-4
Electronic_ISBN
8164-2284
Type
conf
DOI
10.1109/IEDM.2008.4796852
Filename
4796852
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