A high speed programmable digital FIR filter

The implementation of a high-speed, programmable finite impulse response (FIR) filter using coefficients consisting of two power-of-two terms is presented. The area and speed performance figures for this application-specific IC (ASIC) demonstrate the superiority of this architecture for high-speed and high-density implementation. This implementation was developed using a relatively primitive CMOS process. Simple λ-rule scaling suggests that by using a 1.25-μm and double-level metal process of the same die size, this architecture will allow the implementation of a filter of approximately 200 taps operating at a 10-MHz sampling rate