• DocumentCode
    2933391
  • Title

    Engineering a planar NAND cell scalable to 20nm and beyond

  • Author

    Ramaswamy, Nirmal ; Graettinger, Thomas ; Puzzilli, Giuseppina ; Haitao Liu ; Prall, Kirk ; Gowda, Suraj ; Furnemont, Arnaud ; Changhan Kim ; Parat, K.

  • fYear
    2013
  • fDate
    26-29 May 2013
  • Firstpage
    5
  • Lastpage
    8
  • Abstract
    Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell.
  • Keywords
    NAND circuits; floating point arithmetic; high-k dielectric thin films; integrated memory circuits; optimisation; Intel-Micron; floating gate NAND memory cell; high-K-metal gate planar cell; nanocrystal cell; nitride cell; optimization; planar NAND cell; planar floating gate cell; size 20 nm; Capacitors; Interference; Logic gates; Metals; Silicon; 1Xnm; 20nm; Planar NAND cell;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Workshop (IMW), 2013 5th IEEE International
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    978-1-4673-6168-2
  • Type

    conf

  • DOI
    10.1109/IMW.2013.6582080
  • Filename
    6582080