Improved power scaling issue for pipeline ADC

Author

Chen, Tingting ; Li, Zheying ; Li, Bo ; Li, Yuemei ; Wang, Chunlei ; Wang, Jianjian

Author_Institution

Beijing Union Univ., Beijing

fYear

2007

fDate

Nov. 28 2007-Dec. 1 2007

Firstpage

454

Lastpage

457

Abstract

In this paper an improved method to design a power optimized pipeline ADC is presented. By analyzing the architecture of SHA and the dependency of power on SNR, supply voltage and sampling rate, the flowchart instructing the design of pipeline ADC is put forward which simultaneously determines the resolution distribution, the optimum value for capacitors scaling factor, the parameter of OTA in each stage. A 0.18-mum 10-bit 80-MS/s CMOS prototype achieves 58.1 dB SNDR is implemented to validate the power scaling approach.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; pipeline processing; CMOS prototype; analog-to-digital converter; capacitors scaling factor; pipeline ADC; power scaling; resolution distribution; size 0.18 mum; Capacitors; Energy consumption; Flowcharts; Pipelines; Power dissipation; Prototypes; Sampling methods; Signal processing; Signal resolution; Voltage; comparator; pipeline ADC; power scaling; sample and hold amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. International Symposium on

Conference_Location

Xiamen

Print_ISBN

978-1-4244-1447-5

Electronic_ISBN

978-1-4244-1447-5

Type

conf

DOI

10.1109/ISPACS.2007.4445922

Filename

4445922