DocumentCode
2933673
Title
Highly scalable and manufacturable heterogeneous charge trap NAND technology
Author
Haddad, Sandro ; Fang, Shao-Yun ; Chang, Kuo-Pin ; Shetty, Sachin ; Chen, Ci ; Kim, Unha ; Fang, Tao ; Ortiz, S. ; Thurgate, T. ; Ramsbey, M. ; Kang, I. ; Janai, M. ; Neo, J. ; Singh, Praveen Kumar ; Nagatani, G. ; Samqui, A. ; Sugino, R. ; Hui, Alexis ;
Author_Institution
Spansion, Inc., Sunnyvale, CA, USA
fYear
2013
fDate
26-29 May 2013
Firstpage
60
Lastpage
63
Abstract
For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product performance, reliability, and manufacturability demonstrated at the 43nm node, in conjunction with the planar cell architecture have laid the foundation for scaling to <; 20nm.
Keywords
NAND circuits; circuit reliability; electron traps; random-access storage; silicon compounds; NAND technology; SiN; heterogeneous charge trap memory; planar cell architecture; product performance; reliability; silicon rich nitride storage layer; size 43 nm; Computer architecture; Films; Interference; Logic gates; Nonvolatile memory; Programming; Silicon; Charge Trap Memory; Heterogeneous nitride; NAND; SiRN; Silicon-Rich Nitride;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2013 5th IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4673-6168-2
Type
conf
DOI
10.1109/IMW.2013.6582098
Filename
6582098
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