Author :
Kawasumi, A. ; Kushida, K. ; Hara, Hideki ; Unekawa, Y. ; Abe, Kiyohiko ; Ikegami, Kenshin ; Noguchi, Hiroki ; Kitagawa, Eiji ; Kamata, Chikayoshi ; Kashiwada, Shintaro ; Kato, Yu ; Saida, Daisuke ; Shimomura, Naoharu ; Ito, Junichi ; Fujita, S.
Abstract :
Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin.
Keywords :
MRAM devices; cache storage; SRAM; STT MRAM; adaptive pulse-driven read current control; circuit techniques; cross-coupled hierarchical switch; nonvolatile L2 cache memory; voltage generator; Cache memory; Frequency estimation; Generators; Power demand; Random access memory; Switches; Transistors; Cache memory; MRAM; Normally-off-type;
