DocumentCode
2933989
Title
A logic-based embedded DRAM with novel cell structure and dynamically adaptive refresh for long data retention, zero data availability penalty and high yield
Author
Xue, X.Y. ; Meng, Chun ; Dong, C.L. ; Chen, Bing ; Lin, Y.Y. ; Huang, R. ; Zou, Q.T. ; Wu, J.G.
Author_Institution
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
fYear
2013
fDate
26-29 May 2013
Firstpage
132
Lastpage
134
Abstract
Three techniques are proposed and verified on a logic-based 128kb embedded DRAM macro. Novel 2T gain cell of asymmetric junction increases data retention by 21X. Dynamically adaptive staggered refresh achieves zero data availability penalty and improves yield significantly. 60% smaller cell size than 6T SRAM and 25-30% refresh power reduction are obtained.
Keywords
logic circuits; random-access storage; 2T gain cell; asymmetric junction; cell structure; data retention; logic-based embedded DRAM; power reduction; Availability; Junctions; Monitoring; Random access memory; Temperature measurement; Temperature sensors; Transistors; embedded DRAM; refresh; retention;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2013 5th IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4673-6168-2
Type
conf
DOI
10.1109/IMW.2013.6582116
Filename
6582116
Link To Document