Equalization system including clock recovery application to MAC/Packet family signals

An equalization system including clock recovery is presented. This equalization system comprises two different parts: a classical part, that is, a mean square error time domain equalizer, and a specific part, which provides the means of ensuring clock recovery included in the equalizer loop. The main functions are a fixed phase of the sampling clock simulation and a stop criterion derived from the bit error rate (BER) by using correlation of duobinary data. Results show that the system improves the BER. It can be used to get the required sampling clock and synchronization acquisition, even with severely distorted signals. The system is stable for all the perturbations induced by the channel transmission for the D2-MAC/Packet signal