Vertical polysilicon Pinch-Off FET for 3D memory technology: Feasibility and electrical performance

Author

Congedo, G. ; Toledano-Luque, Maria ; Arreghini, A. ; Kar, Gouri Sankar ; Tang, Bo-Hui ; Degraeve, Robin ; Van Aerde, S. ; Kim, Wonhee ; Van den bosch, G. ; Van Houdt, J.

Author_Institution

imec, Leuven, Belgium

fYear

2013

fDate

26-29 May 2013

Firstpage

159

Lastpage

162

Abstract

The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D memory technology is demonstrated. The proposed device is fully compatible with the standard punch-and-plug process, as required for bit cost scaling. We show that the depletion mode POFET cell with an optimized n-doping level, fabricated in our 3D-SONOS test vehicle has a significantly higher read current than conventional undoped poly-Si inversion mode device. Furthermore, the implications of different ONO thicknesses in the memory performance are analyzed and discussed into detail.

Keywords

field effect transistors; random-access storage; semiconductor doping; silicon; 3D memory technology; 3D-SONOS test vehicle; bit cost scaling; depletion mode POFET cell; electrical performance; n-doping level; standard punch-and-plug process; undoped poly Si inversion mode device; vertical polysilicon pinch-off FET; Charge carrier processes; Doping; Junctions; Logic gates; Performance evaluation; Silicon; Temperature measurement; Non Volatile Memory (NVM); ONO; poly-Si; program/erase; retention;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2013 5th IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6168-2

Type

conf

DOI

10.1109/IMW.2013.6582123

Filename

6582123