Towards DRAM-Flash hybrid: Dual-speed low-voltage ferroelectric and charge memory

Author

Rajwade, Shantanu R. ; Auluck, Kshitij ; Jayant, Krishna ; Kan, Edwin C. ; Naoi, Taro A. ; Van Dover, R.B.

Author_Institution

Electr. & Comput. Eng, Cornell Univ., Ithaca, NY, USA

fYear

2013

fDate

26-29 May 2013

Firstpage

166

Lastpage

169

Abstract

We present a one-transistor low-voltage hybrid ferroelectric and charge nonvolatile memory with dual switching speed. The device can be operated in two modes: 1) fast (10 ns-1 μs) DRAM-like mode with hours of retention, benefiting from ferroelectric (FE) switching, and 2) slow Flash-like mode (100 μs-1 ms) with long retention, resulting from charge injection. The combined FE and charge mechanisms offer additive memory window (MW) and cancelling retention fields. The hybrid memory was fabricated with PZT as the FE and Au nanocrystals (NCs) as charge storage nodes. Simulations incorporating FE switching dynamics were performed to corroborate the two-step program process as well as provide useful insight into hybrid design.

Keywords

DRAM chips; ferroelectric storage; ferroelectric switching; flash memories; gold; iron; lead compounds; oxygen compounds; titanium compounds; zirconium compounds; Au; DRAM-flash hybrid memory; FE switching; Fe; MW; NC; PZT; additive memory window; charge injection; charge nonvolatile memory; charge storage nodes; dual switching speed; dual-speed low-voltage ferroelectric memory; ferroelectric switching; hybrid design; nanocrystals; one-transistor memory; retention fields cancellation; time 10 ns to 1 mus; time 100 mus to 1 ms; two-step program; Gold; Iron; Logic gates; Nonvolatile memory; Predictive models; Random access memory; Switches; DRAM; Flash; ferroelectric; hybrid;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2013 5th IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6168-2

Type

conf

DOI

10.1109/IMW.2013.6582125

Filename

6582125